- Von Neumann Machine repeatedly executes the 'fetch->decode->execution' cycle.
- When we first press the switch button, we should decide which program to executue first, and this program is called 'Initialization program'.
- The initialization program is stored in the ROM BIOS (Basic Input/Output System), which is the first location to fetch, also called the 'Reset Vector'.
- After the first fetch operation by the CPU at reset vector address, it jumps to system initialization routine.
- Initializtion routine includes memory tests, controller initializations, interrupt vector initialization, and then jump to OS load.
- While RAM memory(Random Access Memory) is volatile while the ROM memory(Read Only Memory) is non-volatile.
- Booting is a series of task to be ready on OS control.
- After initialization routine, jumping to OS load, we read a boot record onto RAM memory.
- Boot record is a routine to read the basic OS files and this is done by the bootstrap loader.
- After reading a boot record, control is transferred to the OS commander processor.
- For communication between the Von Neumann Machine and I/O devices, there exists special instructions.
- 'In xxx' means data moving from [xxx] to EAX.
- 'Out xxx' means data moving from EAX to [xxx].
- I/O devices has a I/O address assigned, and 'I/O address mapping' means assigning an address to devices.
- There exists two ways of I/O operations, the first is 'I/O-mapped I/O', and the other is 'Memory-mapped I/O'.
- 'I/O mapped I/O' is setting a special I/O instruction, and Intel processors uses this method.
- 'Memory mapped I/O' is in the CPU's perspective, thinking I/O devices share memory address space, and the control registers manipulate the I/O device just like RAM memory. ARM processors uses this method.
- Decoder gets address as input and outputs 1 as select signal if the connected I/O device is assigned the specific address.
- Like in the Von Neumann Machine how the CPU and Memory interacted with each other, we use IOR, IOW, Data bus for communication between the CPU and I/O devices.
- The following procedure is when data is sent to I/O device.
- When an I/O device is selected by the CPU (when select signal 1 is sent from decoder), it is sent to the Command Register inside the I/O Controller.
- Then, with the Data bus, the data is sent to the Data Register inside the I/O Controller.
- Lastly, after all the operation is done, the Status Register is set to 1.
- There exists 3 ways of receiving data(data transfer) from the I/O device.
- Program Controlled I/O is a data transfer mode of the CPU asking the I/O device whether it is ready or not.
- This has a big problem that computers can fall into infinite loop.
- This method is no longer used.
- Interrupt driven I/O is a data transfer mode of the I/O device sending a signal to the CPU when I/O operation is ready.
- The process of interrupting the CPU is done using the INT_RQ line.
- The I/O device sends 1 if it has a process for the CPU to do (which is interrupting), and CPU in response sends 1 to IACK.
- In order to check if there is any interrupt request, CPU checks for interrupt pending before fetching next instruction.
- If an INT was requested, CPU stops the execution of current program, and save the current PC in a stack.
- The specific operation that was requested by the I/O device is called the interrupt service routine(ISR).
- Using vector to jump to ISR, the CPU executes ISR, and after finishing the service, RET instruction is executed to finish.
- The stack is a data structure allocated to model, which is a LIFO(Last In First Out) structure.
- There exists two ways of identifying which I/O device interupted the CPU.
- 'Polling method' is a method of identifying the device by polling all I/O device in predetermined order.
- This might be simple but is slow and therefore not used.
- 'Vectorized method' is a method that each I/O device is assigned a special i.d. code(vector).
- When a device requests an INT, it places its vector(i.d. code) on the data bus, and therefore the CPU identifies the interrupting device by reading the code.
- Usually the vector is the starting address of service routine.
- For simultaneous request, there should be a method for selecting one device over the order, meaning priority.
- In the polling method, priority is the order to poll.
- In the vectorized method, we decide the priority using the 'Interrupt acknowledge daisy chain'.
- Interrupt acknowledge daisy chain means deciding the priority order based on the order that INT_AK arrived.
- If the device receives an INT_AK from CPU, it places its vector on the bus and then the CPU services that.
- Direct Memory access(DMA) is a data transfer mode with no CPU intervention.
- When a large block of data is moved, it is inefficient for the data to pass by the CPU, and it would rather be efficient for the data to move directly from the memory to I/O device.
- DMAC requests the control of bus from the CPU, and the DMA controller is becoming the bus master.
- When CPU no longer needs the bus, it acknowledges it by using the DMA_ACK.
- There exists a Word Count Register(WCR) which is decremented after each transfer of data between memory and I/O. If WCR=0, the DMAC returns control to the CPU.
- Along with the Word Count Register, the Block Starting Address Register(BSAR) is loaded.
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